Refereed Journal Papers

• H. Nagano, T. Fujiwara and T. Kasami, "Average Complexity Evaluation of an MLD Algorithm Using the Trellis Structure for a Linear Block Code", IEICE Trans. Fundamentals , vol. E78-A, no. 9, pp. 1209-1214, Sep., 1995.

Refereed Conference Papers

• H. Nagano, A. Matsuura and A. Nagoya, "An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture", Proc. of 6th Reconfigurable Architectures Workshop (RAW '99) in IPPS/SPDP'99 Workshops - Parallel and Distributed Processing, pp. 670-678, Springer, Apr., 1999.
• A. Matsuura, H. Nagano and A. Nagoya, "A Method for Implementing Fractal Image Compression on Reconfigurable Architecture", Proc. of ACM International Symposium on Field-Programmable Gate Arrays (FPGA'99), p. 251, Feb., 1999.
• H. Nagano, T. Suyama and A. Nagoya, "Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach", Proc. of Asia and South Pacific Design Automation Conference 1999 (ASP-DAC '99), pp. 161-164, Jan., 1999.
• H. Nagano, T. Suyama and A. Nagoya, "Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs", Proc. of International Symposium on Field Programmable Gate Arrays (FPGA '98), p. 261, Feb., 1998.
• H. Yamamoto, H. Nagano, T. Fujiwara and T. Kasami, "Recursive MLD Algorithm Using the Detail Trellis Structure for a Linear Block Code and Its Average Complexity Analysis", Proc. of the International Symposium on Information Theory and Its Applications, pp. 704-708, Sep., 1996.

Non-refereed Conference Papers

• 永野 秀尚, 須山 敬之, 名古屋 彰, "再構成可能なハードウェアを用いた線形ブロック符号の性能評価の高速化", 電子情報通信学会 技術研究報告, VLD98-144, ICD98-290, pp. 25-32, 1999年3月.
• 松浦 昭洋, 永野 秀尚, 名古屋 彰, "フラクタル画像圧縮の再構成可能アーキテクチャによる実現法", 電子情報通信学会 技術研究報告 , CPSY98-83, pp. 15-22, 1998年9月.
• 永野 秀尚，須山 敬之，名古屋 彰，上田 義勝，中村 行宏 "PARTHENONとFPGAマッピングツールの連携に関する検討 -GateFieldの場合-"， 第11回パルテノン研究会資料集, pp. 67-76, 1997年12月．
• T. Koumoto, H. Nagano, T. Takata, T. Kasami, T. Fujiwara and S. Lin, "An Iterative Soft-Decision Decoding Algorithm", Proc. of the 18th Symposium on Information Theory and Its Applications (SITA '95), pp. 557-560, Oct., 1995.
• H. Nagano, T. Fujiwara and T. Kasami, "A Decoding Algorithm for a Linear Block Code Using the Detailed Structure of its Trellis Diagram with Partial Search", Proc. of the 18th Symposium on Information Theory and Its Applications (SITA '95), pp. 449-452, Oct., 1995.
• T. Koumoto, H. Nagano, T. Takata, T. Kasami, T. Fujiwara and S. Lin, "A New Iterative Soft-Decision Decoding Algorithm", Technical Report of IEICE, IT-95-28, pp. 19-24, July, 1995.
• H. Nagano, T. Fujiwara and T. Kasami, "Complexity Evaluation of an MLD Algorithm for a Linear Block Code Using Its Trellis Structure ", Proc. of the 17th Symposium on Information Theory and Its Applications (SITA '94), pp. 209-212, Dec., 1994.

Theses

• H. Nagano, "A Suboptimum Decoding Algorithm for a Linear Code Using its Detail Trellis Structure with Partial Search", Master Thesis, Department of Information and Computer Science, Faculty of Engineering Science, Osaka University, Mar., 1996.
• 永野 秀尚, "線形符号用最尤復号プログラムの高速化 -トレリスダイアグラムの内部構造の利用-", 特別研究報告, 大阪大学基礎工学部情報工学科, 1994年3月.