Journal Publications
- H. Sawada, S. Yamashita and A. Nagoya,
"Restructuring Logic Representations with Simple Disjunctive Decompositions",
IEICE Trans. Fundamentals,
Vol. E81-A, No. 12, pp. 2538-2544, Dec. 1998.
- S. Yamashita, H. Sawada and A. Nagoya,
"An Efficient Method for Finding an Optimal Bi-Decomposition",
IEICE Trans. Fundamentals,
Vol. E81-A, No. 12, pp. 2529-2537, Dec. 1998.
- H. Sawada, T. Suyama and A. Nagoya,
"Logic Synthesis for Look-Up Table based FPGAs
using Functional Decomposition and Boolean Resubstitution",
IEICE Trans. Information and Systems,
Vol. E80-D, No. 10, pp. 1017-1023, Oct. 1997.
(Paper: PDF)
- H. Sawada, Y. Takenaga and S. Yajima,
"On the Computational Power of Binary Decision Diagrams",
IEICE Trans. Information and Systems,
Vol. E77-D, No. 6, pp. 611-618, Jun. 1994.
Conference Publications
- H. Sawada, S. Yamashita and A. Nagoya,
"An Efficient Method for Generating Kernels on Implicit Cube Set
Representations", Workshop Handouts of International Workshop
on Logic Synthesis (IWLS '99), pp. 260-263, June 1999.
(Paper: PDF)
- S. Yamashita, H. Sawada and A. Nagoya,
"An Integrated Approach for Synthesizing LUT Networks",
Proc. of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99),
pp. 136-139, Feb. 1999.
- H. Sawada, S. Yamashita and A. Nagoya,
"Efficient Methods for a Simple Disjoint Decomposition and
Non-Disjoint Bi-Decomposition",
Booklet 7th International Workshop on Post-Binary ULSI Systems,
pp. 34-37, May 1998.
(Handout: PDF)
- H. Sawada, S. Yamashita and A. Nagoya,
"Restructuring Logic Representations with Easily
Detectable Simple Disjunctive Decompositions",
Proc. Design, Automation and Test in Europe Conf. (DATE '98),
pp. 755-759, Feb. 1998.
(Paper: PDF)
- S. Yamashita, H. Sawada and A. Nagoya,
"New Methods to Find Optimal Non-Disjoint Bi-Decompositions",
Proc. of Asia and South Pacific Design Automation Conference 1998
(ASP-DAC '98), pp. 59-68, Feb. 1998.
- T. Suyama, M. Yokoo, and H. Sawada,
"Solving Satisfiability Problems Using Logic Synthesis
and Reconfigurable Hardware",
Proc. of the 31st Annual Hawaii International Conference on System
Sciences (HICSS-31), Vol. VII, pp. 179-186, Jan. 1998.
- H. Sawada, S. Yamashita and A. Nagoya,
"Restricted Simple Disjunctive Decompositions
Based on Grouping Symmetric Variables",
Proc. the Seventh Great Lakes Symposium on VLSI (GLS-VLSI '97),
pp. 39-44, Mar. 1997.
- S. Yamashita, H. Sawada and A. Nagoya,
"A New Method to Express Functional Permissibilities
for LUT based FPGAs and Its Applications",
Proc. Int'l Conf. Computer-Aided Design (ICCAD '96),
pp. 254-261, Nov. 1996.
- T. Suyama, M. Yokoo, and H. Sawada,
"Solving Satisfiability Problems on FPGAs",
Proc. of the 6th International Workshop on Field
Programmable Logic and Applications (FPL '96), pp. 136-145, Sep. 1996.
- M. Yokoo, T. Suyama, H. Sawada,
"Solving Satisfiability Problems using Field Programmable Gate Arrays:
First Results",
Second International Conference on Principles and Practice
of Constraint Programming (CP-96), pp. 497-509, Aug. 1996.
- T. Suyama, H. Sawada and A. Nagoya,
"LUT-based FPGA Technology Mapping using Permissible Functions",
Proc. of the 9th International Conference on VLSI Design
(VLSI Design '96), pp. 215-218, Jan. 1996.
- H. Sawada, T. Suyama and A. Nagoya,
"Logic Synthesis for Look-Up Table based FPGAs using
Functional Decomposition and Support Minimization",
Proc. Int'l Conf. Computer-Aided Design (ICCAD '95),
pp. 353-358, Nov. 1995.
- H. Sawada, T. Suyama and A. Nagoya,
"Logic Synthesis Method for Look-Up Table Architectures
using Functional Decomposition and Support Minimization",
Proc. SASIMI,
pp. 161-168, Aug. 1995.
- N. Ishiura, H. Sawada and S. Yajima,
"Minimization of Binary Decision Diagrams based on Exchanges of Variables",
Proc. Int'l Conf. Computer-Aided Design (ICCAD '91),
pp. 472-475, Nov. 1991.
Theses
- "Computational Power of Binary Decision Diagrams",
Master Thesis, Department of Information Science,
Faculty of Engineering, Kyoto University, Feb. 1993.
Hiroshi Sawada <sawada@cslab.kecl.ntt.co.jp>
Last modified: Tue Nov 2 11:28:36 1999