--- simulation modules:
r256_8                          (circuit         )
inc8                            (circuit         )
cla8                            (circuit         )
top                             (module          )
cpu                             (module          )

--- facilities of top module:
/                               (module          )
  cpu                             (submodule       )
  ram                             (submodule       )
  start                           (instr input     )

--- simulation start:

input pins| internal state, signals                   | output pins, memory
CLK  start| pc a  x  c op1 op2 md if     exec  ift ext| adrs dti dto ff
---------------------------------------------------------------------------
0    0    | 00 uu uu u uu  uu  uu fetch1 exec1 0   0  | zz   zz  zz  00
1    1    | 00 uu uu u uu  uu  uu fetch1 exec1 0   0  | zz   zz  zz  00
2    0    | 00 uu uu u uu  uu  uu fetch1 exec1 1   0  | 00   83  zz  00
3    0    | 01 uu uu u 83  uu  uu fetch2 exec1 1   0  | 01   fd  zz  00
4    0    | 02 uu uu u 83  fd  uu fetch1 exec1 0   1  | zz   zz  zz  00
5    0    | 02 uu fd u 83  fd  uu fetch1 exec1 1   0  | 02   01  zz  00
6    0    | 03 uu fd u 01  fd  uu fetch1 exec1 0   1  | fd   12  zz  00
7    0    | 03 12 fd u 01  fd  uu fetch1 exec1 1   0  | 03   08  zz  00
8    0    | 04 12 fd u 08  fd  uu fetch1 exec1 0   1  | zz   zz  zz  00
9    0    | 04 12 fd 0 08  fd  uu fetch1 exec1 1   0  | 04   83  zz  00
10   0    | 05 12 fd 0 83  fd  uu fetch2 exec1 1   0  | 05   fe  zz  00
11   0    | 06 12 fd 0 83  fe  uu fetch1 exec1 0   1  | zz   zz  zz  00
12   0    | 06 12 fe 0 83  fe  uu fetch1 exec1 1   0  | 06   0b  zz  00
13   0    | 07 12 fe 0 0b  fe  uu fetch1 exec1 0   1  | fe   34  zz  00
14   0    | 07 12 fe 0 0b  fe  34 fetch1 exec2 1   1  | 07   83  zz  00
15   0    | 08 46 fe 0 83  fe  34 fetch2 exec1 1   0  | 08   ff  zz  00
16   0    | 09 46 fe 0 83  ff  34 fetch1 exec1 0   1  | zz   zz  zz  00
17   0    | 09 46 ff 0 83  ff  34 fetch1 exec1 1   0  | 09   02  zz  00
18   0    | 0a 46 ff 0 02  ff  34 fetch1 exec1 0   1  | ff   zz  46  00
19   0    | 0a 46 ff 0 02  ff  34 fetch1 exec1 1   0  | 0a   07  zz  46
20   0    | 0b 46 ff 0 07  ff  34 fetch1 exec1 0   1  | zz   zz  zz  46
21   0    | 0b 46 ff 1 07  ff  34 fetch1 exec1 1   0  | 0b   8d  zz  46
22   0    | 0c 46 ff 1 8d  ff  34 fetch2 exec1 1   0  | 0c   0b  zz  46
23   0    | 0d 46 ff 1 8d  0b  34 fetch1 exec1 0   1  | zz   zz  zz  46
24   0    | 0b 46 ff 1 8d  0b  34 fetch1 exec1 1   0  | 0b   8d  zz  46
25   0    | 0c 46 ff 1 8d  0b  34 fetch2 exec1 1   0  | 0c   0b  zz  46
26   0    | 0d 46 ff 1 8d  0b  34 fetch1 exec1 0   1  | zz   zz  zz  46