/*=======================================================================*/
    /*IMLIG,1998.01.07,timer8.sfl,timer example (source PARTHENON WWW page)  */
    /*=======================================================================*/
    /*-----------------------------------------------------------------------*/
    /*interface declaration of 8-bit decrementor dec8 (submodule)            */
    /*-----------------------------------------------------------------------*/
  7 declare dec8 {
  8   input    in<8>;
  9   output   out<8>;
 10   instrin  do;
 11   instr_arg do(in);
 12 }/*dec8*/
 13 
    /*-----------------------------------------------------------------------*/
    /*circuit definition of 8-bit decrementor dec8                           */
    /*-----------------------------------------------------------------------*/
 17 circuit dec8 {
 18   input   in<8>;
 19   output  out<8>;
 20   instrin do;
 21 
 22   instruct do out= in+ 0xff;   /*two's complement: in-0x01= in+^0x01+1*/
 23 }/*dec8*/
 24 
    /*-----------------------------------------------------------------------*/
    /*module definition of timer8 (top module)                               */
    /*-----------------------------------------------------------------------*/
 28 module timer8{
    /*-----------------------------*/
    /*facility declaration (F1..F4)*/
    /*-----------------------------*/
      /*I/O facilities (F1)*/
 33   instrin    SET, RESET;
 34   input      INIT<8>;
 35   instrout   EXPIRE, ENABLE;
 36   output     COUNT<8>;
 37 
      /*internal facilities (F2)*/
 39   reg        REMAINED<8>;
 40   dec8       DEC;
 41 
      /*argument binding (F3)*/   
 43   instr_arg  ENABLE(COUNT);
 44 
      /*state-machines (F4)*/
 46   stage_name MAIN {
 47     task RUN(REMAINED);
 48   }
    /*----------------------------*/
    /*behavior definition (B1..B3)*/
    /*----------------------------*/
      /*core behavior (B1)*/
 53   par {
 54     ; /*empty statement*/                 
 55   }
 56 
      /*control related behavior (B2)*/
 58   instruct SET par {
 59     generate MAIN.RUN(INIT);
 60   } 
 61 
      /*state-machine behavior (B3)*/
 63   stage MAIN {
 64     state_name  DOWN, ASSERT;
 65     first_state DOWN;
 66 
        /*core behavior (B3.1)*/
 68     if (^RESET) par {
 69       ENABLE(REMAINED);
 70     }
 71 
        /*state behavior (B3.2)*/
 73     state DOWN  any {
 74       RESET | SET : finish;
 75       else        : par {
 76         REMAINED:= DEC.do(REMAINED).out;
 77         if(DEC.out== 0x00) goto ASSERT;
 78       }
 79     }/*DOWN*/
 80 
 81     state ASSERT any {
 82       RESET | SET : par {
 83         goto DOWN; 
 84         finish;
 85       }
 86       else        : EXPIRE();
 87     }/*ASSERT*/
 88   }/*MAIN*/
 89 }/*timer8/