    /*=======================================================================*/
    /*IMLIG,1998.01.07,adder4.sfl, 4-bit full-adder example                  */
    /*=======================================================================*/
    /*-----------------------------------------------------------------------*/
    /*interface declaration of 1-bit full-adder (submodule)                  */
    /*-----------------------------------------------------------------------*/
  7 declare adder1 {
  8   input a, b, cin;        /*data terminals*/
  9   output s, cout;
 10   instrin add;            /*control terminal*/
 11 
 12   instr_arg add(a,b,cin); /*argument binding of add behavior*/
 13 }/*adder1*/
 14 
    /*-----------------------------------------------------------------------*/
    /*module definition of 4-bit full-adder (top module)                     */
    /*-----------------------------------------------------------------------*/
 18 module adder4 {
 19   input A<4>, B<4>, CIN;
 20   output S<4>, COUT;
 21   instrin ADD;
 22 
 23   adder1 ADDER0, ADDER1, ADDER2, ADDER3;  /*module instantiation*/
 24   sel CARRY1, CARRY2, CARRY3;             /*internal signal*/
 25 
 26   instruct ADD par{                       /*definition of ADD behavior*/
 27     S=   ADDER3.add(A<3>,B<3>,CARRY3).s   /*S<3>     ||= concatenation*/
 28       || ADDER2.add(A<2>,B<2>,CARRY2).s   /*S<2>*/
 29       || ADDER1.add(A<1>,B<1>,CARRY1).s   /*S<1>*/
 30       || ADDER0.add(A<0>,B<0>,CIN).s;     /*S<0>*/
 31     COUT= ADDER3.cout;
 32     
 33     CARRY3= ADDER2.cout;
 34     CARRY2= ADDER1.cout;
 35     CARRY1= ADDER0.cout;
 36   }/*ADD*/
 37 }/*adder4*/
 38 
    /*-----------------------------------------------------------------------*/
    /*module definition of 1-bit full-adder                                  */
    /*-----------------------------------------------------------------------*/
    /* truth table of one bit full-adder
    ** input   | output
    ** ----------------
    ** a b cin | s cout
    ** 0 0 0   | 0 0
    ** 0 0 1   | 1 0
    ** 0 1 0   | 1 0
    ** 0 1 1   | 0 1
    ** 1 0 0   | 1 0
    ** 1 0 1   | 0 1
    ** 1 1 0   | 0 1
    ** 1 1 1   | 1 1
    */
 55 module adder1 {
 56   input a, b, cin;
 57   output s, cout;
 58   instrin add;
 59 
 60   instruct add par{           /*definition of add behavior*/
 61     s= a @ b @ cin;           /* @= xor*/
 62     cout= (^a &  b &  cin)    /* ^= not, &= and*/
 63          |( a & ^b &  cin)    /* |= or*/
 64          |( a &  b & ^cin)
 65          |( a &  b &  cin);
 66   }/*add*/
 67 }/*adder1*/
######################################################################
# IMLIG,1998.01.07,adder4.scr, simulator script for SECONDS
sflread adder4.sfl
autoinstall adder4 

#redirect simulation results into file
#speak adder4.sim
#redirect simulation errors into file
#claim adder4.err

print "\n--- simulation modules:\n"
lmc
print "\n--- facilities of top module:\n"
lc

print "\n--- simulation start:\n"
print "\n"
print \
"input pins | internal signals                              | output pins\n"
print \
"A B CIN ADD| ADDER0.a ADDER0.b ADDER0.cin ADDER0.add CARRY1| S COUT\n"
print \
"------------------------------------------------------------------------\n"

rpt_add rpt1 \
"%X %X %B   %B  | %B        %B        %B          %B          %B     | %X %B\n"\
 A  B  CIN  ADD  ADDER0.a ADDER0.b  ADDER0.cin   ADDER0.add CARRY1     S  COUT

set ADD 0B1
set A 0X1; set B 0X1; set CIN 0B0; report do
set A 0X1; set B 0X6; set CIN 0B1; report do
set A 0X7; set B 0X2; set CIN 0B0; report do
set A 0X9; set B 0X8; set CIN 0B0; report do

set ADD 0B0
set A 0X1; set B 0X1; set CIN 0B0; report do
set A 0X1; set B 0X6; set CIN 0B1; report do


--- simulation modules:
adder4                          (module          )
adder1                          (module          )

--- facilities of top module:
/                               (module          )
  A                               (term input      )
  ADD                             (instr input     )
  ADDER0                          (submodule       )
  ADDER1                          (submodule       )
  ADDER2                          (submodule       )
  ADDER3                          (submodule       )
  B                               (term input      )
  CARRY1                          (term internal   )
  CARRY2                          (term internal   )
  CARRY3                          (term internal   )
  CIN                             (term input      )
  COUT                            (term output     )
  S                               (term output     )

--- simulation start:

input pins | internal signals                              | output pins
A B CIN ADD| ADDER0.a ADDER0.b ADDER0.cin ADDER0.add CARRY1| S COUT
------------------------------------------------------------------------
1 1 0   1  | 1        1        0          1          1     | 2 0
1 6 1   1  | 1        0        1          1          1     | 8 0
7 2 0   1  | 1        0        0          1          0     | 9 0
9 8 0   1  | 1        0        0          1          0     | 1 1
1 1 0   0  | z        z        z          0          z     | z z
1 6 1   0  | z        z        z          0          z     | z z
