    /******************************************
    ** (C)Copyright by N.T.T 1993(unpublished) 
    ** All rights are reserved.                
    ******************************************/
    /*-----------------------------------------------------------------------*/
    /*includes  from PARTHENON system library                                */
    /*-----------------------------------------------------------------------*/
  8 %i <r256_8.h>  /*8-bit SRAM memory*/
  9 %i <inc8.h>    /*8-bit incrementor*/
 10 %i <cla8.h>    /*8-bit carry look-ahead adder*/
 11 
    /*-----------------------------------------------------------------------*/
    /*defines                                                                */
    /*-----------------------------------------------------------------------*/
 15 %d LDAI 0x80    /* a <- op2 */
 16 %d LDAX 0x01    /* a <- (x) */
 17 %d STAX 0x02    /* (x) <- a */
 18 %d LDXI 0x83    /* x <- op2 */
 19 %d LDXM 0x84    /* x <- (op2) */
 20 %d STXM 0x85    /* (op2) <- x */
 21 %d INX  0x06    /* x <- x + 1 */
 22 %d SEC  0x07    /* c <- 1 */
 23 %d CLC  0x08    /* c <- 0 */
 24 %d ROLA 0x09    /* c || a <- a || c */
 25 %d COMA 0x0a    /* a <- ^ a */
 26 %d ADCX 0x0b    /* a <- a + (x) + c */
 27 %d ANDX 0x0c    /* a <- a & (x) */
 28 %d BC   0x8d    /* if (c) pc <- op2 */
 29 %d IN   0x0e    /* a <- dti */
 30 %d OUT  0x0f    /* dto <- a */
 31 
    /*-----------------------------------------------------------------------*/
    /*interface declaration of 8-bit cpu                                     */
    /*-----------------------------------------------------------------------*/
 35 declare cpu {
 36   input    dti<8>;
 37   output   dto<8>;
 38   output   adrs<8>;
 39   instrout memory_read;
 40   instrout memory_write;
 41   instrin  start;
 42 }/*cpu*/
 43 
    /*-----------------------------------------------------------------------*/
    /*module definition of top                                               */
    /*-----------------------------------------------------------------------*/
 47 module top {
 48   instrin   start;
 49   cpu       cpu;
 50   r256_8    ram;
 51 
 52   instruct start cpu.start();
 53   instruct cpu.memory_read cpu.dti= ram.read(cpu.adrs).dout;
 54   instruct cpu.memory_write ram.write(cpu.adrs,cpu.dto);
 55 }/*top*/
 56 
    /*-----------------------------------------------------------------------*/
    /*module definition of 8-bit cpu                                         */
    /*-----------------------------------------------------------------------*/
 60 module cpu {
 61   input    dti<8>;
 62   output   dto<8>;
 63   output   adrs<8>;
 64   instrout memory_read;
 65   instrout memory_write;
 66   instrin  start;
 67 
 68   reg_wr   pc<8>;
 69   reg      a<8>;
 70   reg      x<8>;
 71   reg      c;
 72   reg      op1<8>;
 73   reg      op2<8>;
 74   reg      md<8>;
 75   inc8     inc;
 76   cla8     cla;
 77 
 78   instr_arg memory_read(adrs);
 79   instr_arg memory_write(adrs,dto);
 80 
 81   stage_name if {
 82     task ift();
 83   }
 84   stage_name exec {
 85     task ext();
 86   }
 87 
 88   instruct start generate if.ift();
 89 
 90   stage if {
 91     state_name  fetch1;
 92     state_name  fetch2;
 93     first_state fetch1;
 94 
 95     state fetch1 par {
 96       op1:= memory_read(pc).dti;
 97       pc:= inc.do(pc).out;
 98       any {
 99         dti<7>: goto fetch2;
100         else  : relay exec.ext();    /*relay= finish and generate*/
101       }
102     }/*fetch1*/
103 
104     state fetch2 par {
105       op2:= memory_read(pc).dti;
106       pc:= inc.do(pc).out;
107       goto fetch1;
108       relay exec.ext();
109     }/*fetch1*/
110   }/*if*/
111 
112   stage exec {
113     state_name  exec1;
114     state_name  exec2;
115     first_state exec1;
116 
117     state exec1 any {
118       (op1== ADCX) | (op1== ANDX): par {
119         md:= memory_read(x).dti;
120         goto exec2;
121         generate if.ift();
122       }
123       else: par {
124         any {
125           op1== LDAI     : a:= op2;
126           op1== LDAX     : a:= memory_read(x).dti;
127           op1== STAX     : memory_write(x,a);
128           op1== LDXI     : x:= op2;
129           op1== LDXM     : x:= memory_read(op2).dti;
130           op1== STXM     : memory_write(op2,x);
131           op1== INX      : x:= cla.do(0b1,x,0x00).out;
132           op1== SEC      : c:= 0b1;
133           op1== CLC      : c:= 0b0;
134           op1== ROLA     : par { a:= (a || c)<7:0>; c:= a<7>; }
135           op1== COMA     : a:= ^a;
136           (op1== BC) & c : pc:= op2;
137           op1== IN       : a:= dti;
138           op1== OUT      : dto= a;
139         }
140         relay if.ift();
141       }
142     }/*exec1*/
143 
144     state exec2 par {
145       any {
146         op1== ADCX: a:= cla.do(c,a,md).out;
147         op1== ANDX: a:= a & md;
148       }
149       goto exec1;
150       finish;
151     }/*exec2*/
152   }/*exec*/
153 }/*cpu*/
###########################################
# (C)Copyright by N.T.T 1993(unpublished) #
# All rights are reserved.                #
###########################################
sflread cpu.sfl
autoinstall top

#redirect simulation results into file
speak cpu.sim
#redirect simulation errors into file
#claim cpu.err

print "\n--- simulation modules:\n"
lmc
print "\n--- facilities of top module:\n"
lc

#-simulated code----------------------------
# 0x00 LDXI 0xfd
# 0x02 LDAX
# 0x03 CLC
# 0x04 LDXI 0xfe
# 0x06 ADCX
# 0x07 LDXI 0xff
# 0x09 STAX
# 0x0a SEC
# 0x0b BC 0x0b

#-Instruction memory------------------------
memset /ram/cell X00 \
0X83 0Xfd \
0X01 \
0X08 \
0X83 0Xfe \
0X0b \
0X83 0Xff \
0X02 \
0X07 \
0X8d 0X0b

#-Data memory-------------------------------
memset /ram/cell Xfd \
0X12 0X34 0X00

print "\n--- simulation start:\n"
print "\n"

print \
"input pins| internal state, signals                   | output pins, memory\n"
print  \
"CLK  start| pc a  x  c op1 op2 md if     exec  ift ext| adrs dti dto ff\n"
print \
"---------------------------------------------------------------------------\n"

rpt_add rpt1 \
"%2t   %B    | %2X %2X %2X %B %2X  %2X  %2X %6s %5s %B   %B  | %2X   %2X  %2X  %2X\n" \
cpu.start cpu/pc cpu/a cpu/x cpu/c cpu/op1 cpu/op2 cpu/md \
cpu/if cpu/exec cpu/if.ift cpu/exec.ext cpu.adrs cpu.dti cpu.dto \
ram/cell@Xff

sch_add 1 tag "set start 0B1"
report do
forward +26

--- simulation modules:
r256_8                          (circuit         )
inc8                            (circuit         )
cla8                            (circuit         )
top                             (module          )
cpu                             (module          )

--- facilities of top module:
/                               (module          )
  cpu                             (submodule       )
  ram                             (submodule       )
  start                           (instr input     )

--- simulation start:

input pins| internal state, signals                   | output pins, memory
CLK  start| pc a  x  c op1 op2 md if     exec  ift ext| adrs dti dto ff
---------------------------------------------------------------------------
0    0    | 00 uu uu u uu  uu  uu fetch1 exec1 0   0  | zz   zz  zz  00
1    1    | 00 uu uu u uu  uu  uu fetch1 exec1 0   0  | zz   zz  zz  00
2    0    | 00 uu uu u uu  uu  uu fetch1 exec1 1   0  | 00   83  zz  00
3    0    | 01 uu uu u 83  uu  uu fetch2 exec1 1   0  | 01   fd  zz  00
4    0    | 02 uu uu u 83  fd  uu fetch1 exec1 0   1  | zz   zz  zz  00
5    0    | 02 uu fd u 83  fd  uu fetch1 exec1 1   0  | 02   01  zz  00
6    0    | 03 uu fd u 01  fd  uu fetch1 exec1 0   1  | fd   12  zz  00
7    0    | 03 12 fd u 01  fd  uu fetch1 exec1 1   0  | 03   08  zz  00
8    0    | 04 12 fd u 08  fd  uu fetch1 exec1 0   1  | zz   zz  zz  00
9    0    | 04 12 fd 0 08  fd  uu fetch1 exec1 1   0  | 04   83  zz  00
10   0    | 05 12 fd 0 83  fd  uu fetch2 exec1 1   0  | 05   fe  zz  00
11   0    | 06 12 fd 0 83  fe  uu fetch1 exec1 0   1  | zz   zz  zz  00
12   0    | 06 12 fe 0 83  fe  uu fetch1 exec1 1   0  | 06   0b  zz  00
13   0    | 07 12 fe 0 0b  fe  uu fetch1 exec1 0   1  | fe   34  zz  00
14   0    | 07 12 fe 0 0b  fe  34 fetch1 exec2 1   1  | 07   83  zz  00
15   0    | 08 46 fe 0 83  fe  34 fetch2 exec1 1   0  | 08   ff  zz  00
16   0    | 09 46 fe 0 83  ff  34 fetch1 exec1 0   1  | zz   zz  zz  00
17   0    | 09 46 ff 0 83  ff  34 fetch1 exec1 1   0  | 09   02  zz  00
18   0    | 0a 46 ff 0 02  ff  34 fetch1 exec1 0   1  | ff   zz  46  00
19   0    | 0a 46 ff 0 02  ff  34 fetch1 exec1 1   0  | 0a   07  zz  46
20   0    | 0b 46 ff 0 07  ff  34 fetch1 exec1 0   1  | zz   zz  zz  46
21   0    | 0b 46 ff 1 07  ff  34 fetch1 exec1 1   0  | 0b   8d  zz  46
22   0    | 0c 46 ff 1 8d  ff  34 fetch2 exec1 1   0  | 0c   0b  zz  46
23   0    | 0d 46 ff 1 8d  0b  34 fetch1 exec1 0   1  | zz   zz  zz  46
24   0    | 0b 46 ff 1 8d  0b  34 fetch1 exec1 1   0  | 0b   8d  zz  46
25   0    | 0c 46 ff 1 8d  0b  34 fetch2 exec1 1   0  | 0c   0b  zz  46
26   0    | 0d 46 ff 1 8d  0b  34 fetch1 exec1 0   1  | zz   zz  zz  46
