PARTHENON System Introduction (Ver. 2.3.0.6 for SUN Sparc)

This is a quick-intro for the PARTHENON system. After a short overview, the installation procedures and a simple example are demonstrated. Unfortunately, only a part of the documentation is available in English.

For a quick overview I recommend the slide show at:
(../slide/eng/slide_e.htm)
A good introduction can be found at:
(../index_e.htm)

What is PARTHENON?

PARTHENON is composed of 3 main programs: SECONDS, SFLEXP, and OPTMAP. After coding a system in SFL (Structured Function Language), it is simulated with SECONDS. SFL is easy to learn and allows to model synchronous designs very efficiently. SFLEXP performs logic synthesis expanding designs coded in SFL into a generic netlist format. OPTMAP performs minimization of circuits by transduction method (this is implemented in ONSET as a sub kernel of OPTMAP) and technology mapping for target silicon or FPGAs.

How to install the PARTHENON system?

1. Download the binary with your WWW-browser:

Full Release with NEC Cmos, ALTERA, XILINX, GATEFIELD libraries and Tutorial
(parlib2306.tgz)
Partial Release (only with demonstration library)
(par2306.tgz)
IMPORTANT: You also need the license file 'parthe.tar':
(parthe.tar)

Notice, that there are also binaries available for Free BSD and LINUX systems. Their installation works more or less the same. However, they come only with a demonstration library.

2. Extract the PARTHENON system.

% tar xvzf parlib2306.tgz   (in case of GNU tar)

Then, sub-directories are created as follows: (*) ONLY in case of full library version

`par2306/cell_lib.dir`
`....DEMO`	Demonstration cell library (0.8um CMOS)
`....ALTERA (*)`	MAX+plusII (FPGA)
`....GATEFIELD (*)`	GF100K (FPGA)
`....XILINX (*)`	XC3000, XC4000 (FPGA)
`....NEC (*)`	0.3um CMOS library
`par2306/com`	executables plus LICENCE file
`par2306/doc.dir`	documents: (in Japanese!)
`par2306/example.dir`	various design examples
`....Tutorial (*)`	SFL tutorial
`par2306/sfl_lib.dir`	circuit libraries (synthesized netlist)
`par2306/sfl_lib.src`	circuit libraries (SFL source)

You may change the directory name 'par2306' to any name you like.

3. Set an environment variable 'PARTHENON'.

% setenv PARTHENON /.../par2306

Add '$PARTHENON/com' to your search path. You can also modify your '.login' or '.cshrc' to fit your system.

4. Now extract the license file and copy it to the $PARTHENON/com directory:

% tar xvf parthe.tar
% cp parthe.non $PARTHENON/com

How to run PARTHENON?

First let us confirm the installation of your PARTHENON system with a simple example. Simulate a 8 bit CPU (MISC= Minimum Instruction Set Computer!?) coded in 'cpu.sfl' with the corresponding SECONDS simulator file 'cpu.scr':

% cd $PARTHENON/example.dir
% ls cpu.*
% cpu.scr  cpu.sfl
% seconds < cpu.scr

Then, simulation for 'cpu.sfl' will run. You can exit with 'bye'.

SECONDS> bye

Now let's synthesize above design with the 'auto' script. This invokes various makefiles (see '$PARTHENON/com/Makefile' for detailed info) and runs the programs SFLEXP, OPTMAP and ONSET in order to get a design with minimum resources (i.e. gate count). Here is the syntax of the auto script command:

auto <module_name> <result_tag> <foundry> <cell_library>

<module_name>: If using 'auto' the name of SFL file 'NAME.sfl' must be the same as its top module-name 'NAME'
(i.e file= cpu.sfl, top-module= cpu => <module_name>=cpu)
<result_tag>: Choose one of the following:
- nld1|nld2|nld3|ndl4: Possible synthesis stages, full synthesis is nld4
- clean: Cleans work directory for re-synthesis
- ps: Full synthesis (nld4) and generation of circuit postscript file
<foundry>: The directory path of the basic technology library (i.e. contents of PARTHENON/cell_lib.dir/ )
<cell_library>: The directory path of the effective cell library

Here are some examples:

For full synthesis of our design 'cpu.sfl' with the included 0.8um CMOS library (see $PARTHENON/cell_lib.dir/DEMO/demo) type:

% cd $PARTHENON/example.dir
% auto cpu nld4 DEMO demo

Synthesis takes about 3 minutes on a 40 MHz Sparc10. The CPU design holds about 1500 gates. The result cpu.nld is in the newly created directory 'cpu.4th/'. Parthenon also generates a netlist in the standard EDIF format 'cpu.edif200' in the example.dir directory.

To make a postscript file of the circuit diagram type:

% cd $PARTHENON/example.dir
% auto cpu ps DEMO demo

The result is cpu.ps in the top working directory.

To clean the directory for re-synthesis type:

% cd $PARTHENON/example.dir
% auto cpu clean

Where can I get more information?

Try the tutorial in the directory $PARTHENON/example.dir/Tutorial