(Parallel Architecture Refiner Theorized by NTT Original Concept)
|
PARTHENON is an electronic design automation (EDA) system with a behavioral hardware description language SFL as its input. PARTHENON enables behavioral simulation at architecture level and automatic synthesis of logic circuits. The kernel programs of PARTHENON have been completed by incorporating the results of our research over ten years, and we could provide it as a practical EDA system. Now, PARTHENON is widely used in designing advanced ASICs in NTT, and is also used for the aims of education and research on architecture design at many universities. |
Entrance into PARTHENON
Copyright (c) 1998 Nippon Telegraph and Telephone Corporation. All Rights Reserved.
PARTHENON is a trademark of Nippon Telegraph and Telephone Corporation.