Refereed Journal Papers

• H. Nagano, T. Fujiwara and T. Kasami, "Average Complexity Evaluation of an MLD Algorithm Using the Trellis Structure for a Linear Block Code", IEICE Trans. Fundamentals , vol. E78-A, no. 9, pp. 1209-1214, Sep., 1995.

Refereed Conference Papers

• H. Nagano, A. Matsuura and A. Nagoya, "An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture", Proc. of 6th Reconfigurable Architectures Workshop (RAW '99) in IPPS/SPDP'99 Workshops - Parallel and Distributed Processing, pp. 670-678, Springer, Apr., 1999.
• A. Matsuura, H. Nagano and A. Nagoya, "A Method for Implementing Fractal Image Compression on Reconfigurable Architecture", Proc. of International Symposium on Field-Programmable Gate Arrays (FPGA'99), p. 251, Feb., 1999.
• H. Nagano, T. Suyama and A. Nagoya, "Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach", Proc. of Asia and South Pacific Design Automation Conference 1999 (ASP-DAC '99), pp. 161-164, Jan., 1999.
• H. Nagano, T. Suyama and A. Nagoya, "Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs", Proc. of International Symposium on Field Programmable Gate Arrays (FPGA '98), p. 261, Feb., 1998.
• H. Yamamoto, H. Nagano, T. Fujiwara and T. Kasami, "Recursive MLD Algorithm Using the Detail Trellis Structure for a Linear Block Code and Its Average Complexity Analysis", Proc. of the International Symposium on Information Theory and Its Applications, pp. 704-708, Sep., 1996.

Non-refereed Conference Papers

• H. Nagano, T. Suyama and A. Nagoya, "Acceleration of Linear Block Code Evaluations Using Reconfigurable Hardware" (in Japanese), IEICE Technical Report, VLD98-144, ICD98-290, pp. 25-32, Mar., 1999.
• A. Matsuura, H. Nagano and A. Nagoya, "A Method for Implementing Fractal Image Compression on Reconfigurable Architecture" (in Japanese), IEICE Technical Report, CPSY98-83, pp. 15-22, Sep., 1998.
• H. Nagano, T. Suyama, A. Nagoya, Y. Ueda and Y. Nakamura, "A Study of Combining PARTHENON and an FPGA Mapping Tool -In Case of GateField-" (in Japanese), Proc. of the 11th meeting of PARTHENON Technical Society, pp. 67-76, Dec., 1997.
• T. Koumoto, H. Nagano, T. Takata, T. Kasami, T. Fujiwara and S. Lin, "An Iterative Soft-Decision Decoding Algorithm", Proc. of the 18th Symposium on Information Theory and Its Applications (SITA '95), pp. 557-560, Oct., 1995.
• H. Nagano, T. Fujiwara and T. Kasami, "A Decoding Algorithm for a Linear Block Code Using the Detailed Structure of its Trellis Diagram with Partial Search", Proc. of the 18th Symposium on Information Theory and Its Applications (SITA '95), pp. 449-452, Oct., 1995.
• T. Koumoto, H. Nagano, T. Takata, T. Kasami, T. Fujiwara and S. Lin, "A New Iterative Soft-Decision Decoding Algorithm", Technical Report of IEICE, IT-95-28, pp. 19-24, July, 1995.
• H. Nagano, T. Fujiwara and T. Kasami, "Complexity Evaluation of an MLD Algorithm for a Linear Block Code Using Its Trellis Structure ", Proc. of the 17th Symposium on Information Theory and Its Applications (SITA '94), pp. 209-212, Dec., 1994.

Theses

• H. Nagano, "A Suboptimum Decoding Algorithm for a Linear Code Using its Detail Trellis Structure with Partial Search", Master Thesis, Department of Information and Computer Science, Faculty of Engineering Science, Osaka University, Mar., 1996.
• H. Nagano, "An improvement of implementation of Soft Decision Maximum Likelihood decoding simulator by using a structure of the trellis diagram of linear block code" (in Japanese), Bachelor Thesis, Department of Information and Computer Science, Faculty of Engineering Science, Osaka University, Mar., 1994.