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Publications
Refereed Journal Papers
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H. Ito, R. Konishi, H. Nakada, H. Tsuboi, Y. Okuyama and A. Nagoya:
"Dynamically Reconfigurable Logic LSI: PCA-2,"
IEICE Transactions on Information and Systems, Vol. E87-D, No. 8, pp. 2011-2020,
Aug. 2004.
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H. Ito, R. Konishi, H. Nakada, K. Oguri, A. Nagoya and M. Inamori:
"Dynamically Reconfigurable Logic LSI - PCA-1 : The First Realization of Plastic Cell Architecture,"
IEICE Transactions on Information and Systems, Vol. E86-D, No. 5, pp. 859-867,
May 2003.
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M. Inamori, H. Nakada, R. Konishi, A. Nagoya and K. Oguri:
"A Method of Mapping Finite State Machine into PCA Plastic Parts,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E85-A, No. 4, pp. 804-810,
Apr. 2002.
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S. Yamashita, H. Sawada and A. Nagoya:
"A General Framework to Use Various Decomposition Methods for LUT Network Synthesis,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 11, pp. 2915-2922,
Nov. 2001.
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T. Suyama, M. Yokoo, H. Sawada and A. Nagoya:
"Solving Satisfiability Problems using Reconfigurable Hardware (in Japanese),"
Transactions of IEICEJ, Vol. J84-D-I, No. 4, pp. 410-420,
Apr. 2001.
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T. Suyama, M. Yokoo, H. Sawada and A. Nagoya:
"Solving Satisfiability Problems using Reconfigurable Computing,"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, pp. 109-116,
Feb. 2001.
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H. Nagano, A. Matsuura and A. Nagoya:
"An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 1, pp. 372-377,
Jan. 2001.
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H. Sawada, S. Yamashita and A. Nagoya:
"Efficient Kernel Generation based on Implicit Cube Set Representations and Its Applications,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E83-A, No. 12, pp. 2513-2519,
Dec. 2000.
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S. Yamashita, H. Sawada and A. Nagoya:
"SPFD: A New Method to Express Functional Flexibility,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 8, pp. 840-849,
Aug. 2000.
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S. Yamashita, H. Sawada and A. Nagoya:
"SPFD: A New Method to Express Functional Flexibility (in Japanese),"
Transactions of IEICEJ, Vol. J82-A, No. 7, pp. 1047-1056,
Jul. 1999.
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S. Yamashita, H. Sawada and A. Nagoya:
"An Efficient Method for Finding an Optimal Bi-Decomposition,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No. 12, pp. 2529-2537,
Dec. 1998.
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H. Sawada, S. Yamashita and A. Nagoya:
"Restructuring Logic Representations with Simple Disjunctive Decompositions,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E81-A, No. 12, pp. 2538-2544,
Dec. 1998.
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A. Matsuura and A. Nagoya:
"Bit and Word-Level Common Subexpression Elimination for the Synthesis of Linear Computations,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No. 3, pp. 455-461,
Mar. 1998.
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A. Matsuura, M. Yukishita and A. Nagoya:
"A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem,"
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No. 10, pp. 1767-1773,
Oct. 1997.
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H. Sawada, T. Suyama and A. Nagoya:
"Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution,"
IEICE Transactions on Information and Systems, Vol. E80-D, No. 10, pp. 1017-1023,
Oct. 1997.
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Y. Nakamura, K. Oguri, A. Nagoya, M. Yukishita and R. Nomura:
"High-Level Synthesis Design at NTT Systems Labs,"
IEICE Transactions on Information and Systems, Vol. E76-D, No. 9, pp. 1047-1054,
Sep. 1993.
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H. Sekigawa, A. Nagoya, K. Oguri and Y. Nakamura:
"An Efficient Algorithm for Interconnect Elements Assignment (in Japanese),"
Transactions of IEICEJ, Vol. J74-A, No. 7, pp. 1031-1040,
Jul. 1991.
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A. Nagoya, Y. Nakamura, K. Oguri and R. Nomura:
"Multi-Level Logic Optimization for High Level CAD System (in Japanese),"
Transactions of IEICEJ, Vol. J74-A, No. 2, pp. 206-217,
Feb. 1991.
Refereed Conference Papers
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H. Ito, R. Konishi, H. Nakada, Y. Okuyama, A. Nagoya, T. Izumi and Y. Nakamura:
"Asynchronous Dynamically Reconfigurable Logic LSIs Suitable For Technology Scaling,"
Proc. of the 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2004), pp. 458-465,
Oct. 2004.
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Y. Nakane, K. Nagami, T. Shiozawa and A. Nagoya:
"Concept and Implementation of Run-time Resource Management System Operating on Autonomously Reconfigurable Architecture,"
Proc. of 2003 IEEE International Conference on Field-Programmable Technology (FPT '03), pp. 136-143,
Dec. 2003.
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K. Oguri, Y. Shibata and A. Nagoya:
"Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA,"
Proc. of the 8th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2003), Springer LNCS 2823, pp. 54-68,
Sep. 2003 (invited talk).
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H. Ito, R. Konishi, H. Nakada, H. Tsuboi and A. Nagoya:
"Development of Dynamically Reconfigurable Logic LSI: PCA-2 (in Japanese),"
IPSJ/IEICE 2nd Forum on Information Technology (FIT 2003) Information Technology Letters, pp. 53-54,
Sep. 2003.
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H. Ito, R. Konishi, H. Nakada, H. Tsuboi and A. Nagoya:
"Dynamically Reconfigurable Logic LSI designed as Fully Asynchronous System - PCA-2,"
Proc. of COOL Chips VI, p. 84,
Apr. 2003.
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M. Inamori, R. Konishi and A. Nagoya:
"A New Approach to Mapping Finite State Machine into PCA Plastic Parts,"
Proc. of the 10th Workshop on Synthesis And System Integration of MIxed technologies (SASIMI 2001), pp. 178-185,
Oct. 2001.
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Y. Nakane, K. Nagami, T. Shiozawa, N. Imlig, A. Nagoya and K. Oguri:
"Run-time Resource Management for the Dynamically Self-Reconfigurable Architecture PCA (in Japanese),"
Proc. of Design Automation Symposium 2001 (DA Symposium 2001), pp. 67-72,
Jul. 2001.
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Y. Nakane, K. Nagami, T. Shiozawa, N. Imlig, A. Nagoya and K. Oguri:
"Run-time Resource Management for the Dynamically Self-Reconfigurable Architecture PCA,"
Proc. of 1st International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '01), pp. 57-63,
Jun. 2001.
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H. Ito, R. Konishi, H. Nakada, K. Oguri, A. Nagoya, N. Imlig, K. Nagami, T. Shiozawa and M. Inamori:
"Dynamically Reconfigurable Logic LSI - PCA-1,"
Proc. of 2001 Symposium on VLSI Circuits, pp. 103-106,
Jun. 2001.
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H. Sawada, S. Yamashita and A. Nagoya:
"SPFD: A Method to Express Functional Flexibility,"
Booklet of 10th International Workshops on Post-Binary ULSI Systems (ULSI 2001), pp. 19-24,
May 2001 (invited talk).
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H. Nakada, H. Ito, R. Konishi, A. Nagoya, K. Oguri, T. Shiozawa and N. Imlig:
"Self-reorganizing Systems on VLSI Circuits,"
Proc. of 2001 International Symposium on Circuits and Systems (ISCAS 2001), Vol.4, pp. 310-313,
May 2001.
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N. Imlig, T. Shiozawa, K. Nagami, Y. Nakane, R. Konishi, H. Ito and A. Nagoya:
"Scalable Space/Time-shared Stream-Processing on the Run-time Reconfigurable PCA Architecture,"
Proc. of 8th Reconfigurable Architecture Workshop (RAW 2001) associated with 15th Annual International Parallel & Distributed Processing Symposium (IPDPS 2001), pp. 1441-1449,
Apr. 2001.
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M. Inamori, H. Nakada, R. Konishi and A. Nagoya:
"A Method of Mapping Finite State Machine into PCA Plastic Part (in Japanese),"
IEICE The 14th Workshop on Circuits and Systems in Karuizawa, pp. 95-100,
Apr. 2001.
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R. Konishi, H. Ito, H. Nakada, A. Nagoya, K. Oguri, N. Imlig, T. Shiozawa, M. Inamori and K. Nagami:
"PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI,"
Proc. of 7th International Symposium on Asynchronous Circuits and Systems (ASYNC 2001), pp. 54-61,
Mar. 2001.
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T. Shiozawa, N. Imlig, K. Nagami, K. Oguri, A. Nagoya and H. Nakada:
"An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture,"
Proc. of 10th International Conference on Field Programmable Logic and Applications (FPL 2000), Springer LNCS 1896, pp. 805-809,
Aug. 2000.
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K. Aoyama, H. Sawada, A. Nagoya and K. Nakajima:
"A Threshold Logic-based Reconfigurable Element with a Novel Programming Technology,"
Proc. of 10th International Conference on Field Programmable Logic and Applications (FPL 2000), Springer LNCS 1896, pp. 665-674,
Aug. 2000.
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S. Yamashita, H. Sawada and A. Nagoya:
"A Layout Driven Logic Decomposition Model,"
Handouts of 2000 IEEE International Workshop on Logic Synthesis (IWLS 2000), pp. 111-115,
May 2000.
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K. Aoyama, H. Sawada and A. Nagoya:
"A Method for Designing a Circuit with Neuron MOS Transistors Realizing Any Logic Function (in Japanese),"
IEICE The 13th Workshop on Circuits and Systems in Karuizawa, pp. 113-118,
Apr. 2000.
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H. Sawada, S. Yamashita and A. Nagoya:
"A Boolean Division Algorithm for Implicit Cube Set Representations,"
Proc. of the 9th Workshop on Synthesis And System Integration of MIxed technologies (SASIMI 2000), pp. 279-283,
Apr. 2000.
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S. Yamashita, H. Sawada and A. Nagoya:
"An Efficient Framework of Using Various Decomposition Methods to Synthesize LUT Networks and Its Evaluation,"
Proc. of Asia and South Pacific Design Automation Conference 2000 (ASP-DAC 2000), pp. 253-258,
Jan. 2000.
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T. Suyama, M. Yokoo and A. Nagoya:
"Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation,"
Proc. of 5th International Conference on Principles and Practice of Constraint Programming (CP '99), Springer LNCS 1713, pp. 434-445,
Oct. 1999.
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H. Sawada, S. Yamashita and A. Nagoya:
"An Efficient Method for Generating Kernels on Implicit Cube Set Representations,"
Handouts of 1999 IEEE International Workshop on Logic Synthesis (IWLS '99), pp. 260-263,
Jun. 1999.
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A. Matsuura and A. Nagoya:
"Summation Algorithms on Constrained Reconfigurable Meshes,"
Proc. of International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN '99), pp. 400-405,
Jun. 1999.
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H. Sawada, S. Yamashita and A. Nagoya:
"An Efficient Method for Generating Kernels on Implicit Cube Set Representations (in Japanese),"
IEICE The 12th Workshop on Circuits and Systems in Karuizawa, pp. 331-336,
Apr. 1999.
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A. Matsuura and A. Nagoya:
"An Optimal Algorithm for Summing Binary Numbers on Reconfigurable Meshes of a Linear-Delay Model (in Japanese),"
IEICE The 12th Workshop on Circuits and Systems in Karuizawa, pp. 481-486,
Apr. 1999.
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H. Nagano, A. Matsuura and A. Nagoya:
"An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture,"
PProc. of 6th Reconfigurable Architecture Workshop (RAW '99) associated with 13th International Parallel Processing Symposium & 10th Symposium on Parallel and Distributed Processing (IPPS/SPDP '99), Springer LNCS 1586, pp. 670-678,
Apr. 1999.
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T. Suyama, M. Yokoo and A. Nagoya:
"Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation Heuristic,"
Proc. of 6th Reconfigurable Architecture Workshop (RAW '99) associated with 13th International Parallel Processing Symposium & 10th Symposium on Parallel and Distributed Processing (IPPS/SPDP '99), Springer LNCS 1586, pp. 709-711,
Apr. 1999.
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S. Yamashita, H. Sawada and A. Nagoya:
"An Integrated Approach for Synthesizing LUT Networks,"
Proc. of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), pp. 136-139,
Feb. 1999.
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A. Matsuura, H. Nagano and A. Nagoya:
"A Method for Implementing Fractal Image Compression on Reconfigurable Architecture,"
Proc. of ACM International Symposium on Field-Programmable Gate Arrays (FPGA '99), p. 251,
Feb. 1999.
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H. Nagano, T. Suyama and A. Nagoya:
"Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach,"
Proc. of Asia and South Pacific Design Automation Conference 1999 (ASP-DAC '99), pp. 161-164,
Jan. 1999.
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H. Sawada, S. Yamashita and A. Nagoya:
"Efficient Methods for a Simple Disjoint Decomposition and Non-Disjoint Bi-Decomposition,"
Booklet of 7th International Workshop on Post-Binary ULSI Systems (ULSI '98), pp. 34-37,
May 1998.
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H. Sawada, S. Yamashita and A. Nagoya:
"Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions,"
Proc. of Design, Automation and Test in Europe Conference 1998 (DATE '98), pp. 755-759,
Feb. 1998.
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H. Nagano, T. Suyama and A. Nagoya:
"Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs,"
Proc. of Sixth ACM International Symposium on Field Programmable Gate Arrays (FPGA '98), p. 261,
Feb. 1998.
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S. Yamashita, H. Sawada and A. Nagoya:
"New Methods to Find Optimal Non-Disjoint Bi-Decompositions,"
Proc. of Asia and South Pacific Design Automation Conference 1998 (ASP-DAC '98), pp. 59-68,
Feb. 1998.
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A. Matsuura and A. Nagoya:
"Formulation of the Addition-Shift-Sequence Problem and Its Complexity,"
Proc. of the 8th International Symposium on Algorithms and Computation (ISAAC '97), Springer LNCS 1350, pp. 42-51,
Dec. 1997.
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A. Matsuura and A. Nagoya:
"Bit and Word-Level Common Subexpression Sharing for the Multiple Constant Multiplication Problem (in Japanese),"
IEICE The 10th Workshop on Circuits and Systems in Karuizawa, pp. 303-308,
Apr. 1997.
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S. Kimura, M. Yukishita, Y. Itou, A. Nagoya, M. Hirao and K. Watanabe:
"A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor,"
Proc. of the 5th International Workshop on Hardware/Software Co-design (CODES/CASHE '97), pp. 147-151,
Mar. 1997.
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H. Sawada, S. Yamashita and A. Nagoya:
"Restricted Simple Disjunctive Decompositions based on Grouping Symmetric Variables,"
Proc. of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), pp. 39-44,
Mar. 1997.
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A. Matsuura, M. Yukishita and A. Nagoya:
"An Efficient Hierarchical Clustering Method for the Multiple Constant Multiplication Problem,"
Proc. of Asia and South Pacific Design Automation Conference 1997 (ASP-DAC '97), pp. 83-88,
Jan. 1997.
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S. Yamashita, H. Sawada and A. Nagoya:
"A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications,"
Proc. of 1996 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-96), pp. 254-261,
Nov. 1996.
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T. Suyama, H. Sawada and A. Nagoya:
"LUT-based FPGA Technology Mapping using Permissible Functions,"
Proc. of the 9th International Conference on VLSI Design (VLSI Design '96), pp. 215-218,
Jan. 1996.
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H. Sawada, T. Suyama and A. Nagoya:
"Logic Synthesis for Look-Up Table based FPGAs using Functional Decomposition and Support Minimization,"
Proc. of 1995 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-95), pp. 353-358,
Nov. 1995.
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H. Sawada, T. Suyama, M. Yukishita and A. Nagoya:
"Logic Synthesis Method for Look-Up Table Architectures using Functional Decomposition and Support Minimization,"
Proc. of the 5th Workshop on Synthesis And System Integration of MIxed technologies (SASIMI '95), pp. 161-168,
Aug. 1995.
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P. Baglietto and A. Nagoya:
"Design of a SIMD Massively Parallel Computer using a High Level Synthesis System,"
Proc. of 5th International Symposium on IC Technology, Systems & Applications (ISIC-93), pp. 510-514,
Sep. 1993.
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H. Sekigawa, Y. Nakamura, K. Oguri, A. Nagoya and M. Yukishita:
"Multiplexer Assignment after Scheduling and Allocation Steps,"
Proc. of 6th International Workshop on High-Level Synthesis (IWHLS '92), pp. 410-417,
Nov. 1992.
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A. Nagoya, Y. Nakamura and R. Nomura:
"Microprocessor Architecture Design Using High-Level Synthesis System,"
Proc. of International Symposium on Logic Synthesis and Microprocessor Architecture (ISKIT '92), pp. 55-59,
Jul. 1992.
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Y. Nakamura, K. Oguri, A. Nagoya, M. Yukishita and R. Nomura:
"High-Level Synthesis Design at NTT Systems Labs,"
Proc. of Synthesis And SImulation Meeting and International interchange (SASIMI '92), pp. 344-353,
Apr. 1992.
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R. Nomura, K. Oguri, Y. Nakamura and A. Nagoya:
"The Strategy for Reliable ASIC Design in PARTHENON,"
Proc. of the 4th International Forum on ASIC and Transducer Technology (ASICTT '91), pp. 7-12,
May 1991.
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K. Oguri, Y. Nakamura, R. Nomura, A. Nagoya and M. Yukishita:
"PARTHENON: Perfect Harmony between Behavioral Language SFL and Synthesizer,"
IEICE The 4th Workshop on Circuits and Systems in Karuizawa, pp. 198-203,
Apr. 1991.
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R. Nomura, K. Oguri, A. Nagoya and Y. Nakamura:
"A High-Level ASIC CAD System -PARTHENON-,"
Proc. of 2nd Makuhari International Conference on High Technology (MICHT '91), pp. 255-258,
Feb. 1991.
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A. Nagoya, Y. Nakamura, K. Oguri and R. Nomura:
"Multi-Level Logic Optimization for Large Scale ASICs,"
Proc. of the 1990 IEEE International Conference on Computer-Aided Design (ICCAD-90), pp. 564-567,
Nov. 1990.
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Y. Nakamura, K. Oguri, A. Nagoya and R. Nomura:
"A Hierarchical Behavioral Description Based CAD System,"
Proc. of IEEE International Conference EURO ASIC 1990 (EURO ASIC '90), pp. 282-287,
May 1990.
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Y. Nakamura, M. Yukishita, R. Nomura and A. Nagoya:
"Specification Design Expert System for Pipeline Control Architecture,"
Proc. of 1st European Design Automation Conference (EDAC '90), p. 671,
Mar. 1990.
Tutorial Papers and Articles
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A. Nagoya:
"An Introduction to PARTHENON (in Japanese),"
Textbook for the 12th PARTHENON Short Course, pp. 85-96,
Aug. 2004.
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A. Nagoya:
"Utilization Techniques for Logic Optimization Programs in PARTHENON (in Japanese),"
Textbook for the 12th PARTHENON Short Course, pp. 97-122,
Aug. 2004.
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A. Nagoya:
"Autonomously Reconfigurable Hardware : Plastic Cell Architecture (PCA) (in Japanese),"
The Journal of the Institute of Electronics, Information and Communication Engineers, Vol. 87, No. 4, pp. 303-308,
Apr. 2004.
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A. Nagoya:
"An Introduction to PARTHENON (in Japanese),"
Textbook for the 11th PARTHENON Short Course, pp. 129-140,
Aug. 2003.
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T. Suyama, M. Yokoo, H. Sawada and A. Nagoya:
"Solving satisfiability problems by using reconfigurable hardware,"
Electronics and Communications in Japan (Part II: Electronics), Vol. 86, Issue 3, Wiley Periodicals, Inc., pp. 35-46,
Feb. 2003.
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A. Nagoya:
"An Introduction to PARTHENON (in Japanese),"
Textbook for the 10th PARTHENON Short Course, pp. 3-14,
Aug. 2002.
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S. Yamashita, H. Sawada and A. Nagoya:
"A New Notion for Functional Flexibility: A Summary,"
IEEE Circuits and Systems Magazine, Vol. 2, No. 2, pp. 52-54,
2nd qr. 2002.
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A. Nagoya:
"The Plastic Cell Architecture for Dynamically Self-Reconfigurable Computing (in Japanese),"
Journal of the Society of Instrument and Control Engineers, Vol. 40, No. 12, pp. 911-914,
Dec. 2001.
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A. Nagoya:
"An Introduction to PARTHENON (in Japanese),"
Textbook for the 9th PARTHENON Short Course, pp. 3-13,
Aug. 2001.
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A. Nagoya and K. Oguri:
"The Concept of the Plastic Cell Architecture (PCA) (in Japanese),"
NTT R&D, Vol. 49, No. 9, pp. 513-517,
Sep. 2000.
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A. Nagoya, S. Yamashita, M. Inamori and H. Sawada:
"Logic Synthesis and Optimization Methods for Sea-of-LUTs based PCA (in Japanese),"
NTT R&D, Vol. 49, No. 9, pp. 537-545,
Sep. 2000.
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A. Nagoya:
"Design Automation Technologies for Realizing Novel Concurrent Architecture (in Japanese),"
NTT R&D, Vol. 46, No. 2, pp. 153-158,
Feb. 1997.
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Y. Nakamura, K. Oguri, T. Shiozawa, H. Ito, K. Nagami, A. Nagoya, R. Nomura, M. Yukishita, H. Sawada, T. Suyama, A. Matsuura and S. Yamashita:
"PARTHENON for the First Time CD-ROM edition (in Japanese),"
DESIGN WAVE MAGAZINE, No. 3, CQ Publishing,
May 1996.
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A. Nagoya:
"Utilization Techniques for Logic Optimization Programs (in Japanese),"
Transistor Technologies, Vol. 32, No. 3, CQ Publishing, pp. 345-354,
Feb. 1995.
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A. Nagoya:
"Top-Down Design for ASICs using SFL/PARTHENON (in Japanese),"
Interface, Vol. 20, No. 6, CQ Publishing, pp. 196-206,
May 1994.
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A. Nagoya:
"High-level Logic Synthesis System PARTHENON (in Japanese),"
Telecommunications, Vol. 56, No. 562, pp. 66-76,
Oct. 1993.
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Y. Nakamura, K. Oguri, R. Nomura, A. Nagoya and M. Yukishita:
"Research and Development of High-Level Synthesis System based on Behavioral Hardware Description Language (in Japanese),"
Reports of Achievements in Industrialization Awarded the Okochi Memorial Prize 1992, pp. 51-61,
Dec. 1992.
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K. Oguri, Y. Nakamura, R. Nomura and A. Nagoya:
"SFL (in Japanese),"
IPSJ Magazine, Vol. 33, No. 11, pp. 1256-1262,
Nov. 1992.
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A. Nagoya:
"Logic Minimization (in Japanese),"
Journal of Japanese Society for Artificial Intelligence, Vol. 7, No. 3, pp. 540-542,
May 1992.
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S. Shiokawa, Y. Obashi and A. Nagoya:
"DIPS-11/5E Series Mainframes,"
Review of the Electrical Communications Laboratories, Vol. 35, No. 6, pp. 633-641,
Nov. 1987.
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S. Shiokawa, A. Nagoya, A. Matsumoto and K. Tajiri:
"DIPS-11/5E Series Processor (in Japanese),"
Electrical Communications Laboratories Technical Journal, Vol. 36, No. 1, pp. 57-65,
Jan. 1987.
Books
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K. Oguri, A. Nagoya, R. Nomura and M. Yukishita:
"PARTHENON for the First Time (in Japanese),"
CQ Publishing Co., Ltd.,
Sep. 1994,
ISBN 4-7898-3799-8.
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Y. Nakamura and A. Nagoya:
"Design Automation Technologies for ASICs (in Japanese),"
IEICE edit., "ASIC Technology: Fundamentals and Applications", pp. 230-251,
Feb. 1994,
ISBN 4-88552-120-3.
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Y. Nakamura, K. Oguri and A. Nagoya:
"Synthesis from Pure Behavioral Descriptions,"
High-level VLSI Synthesis, R. Camposano and W. Wolf (eds), Kluwer Academic Publishers, pp. 205-229,
Jun. 1991,
ISBN 0-7923-9159-4.