Index
Solving Satisfiability Problems using Field Programmable Gate Arrays: First Results
Main Idea
Why this approach was not considered before?
Why this approach becomes feasible?
FPGA architecture
Definition of SAT
FPGA brings a new dimension to SAT algorithms
Basic enumeration algorithm
Introducing backtracking
Introducing forward checking/unit resolution
Example (parallel checking)
Simulation Result
Flow of logic circuit synthesis
Description in SFL
Logic Circuit Configuration
FPGA hardware system
Trace of execution
Current Status of Implementation
Future works
Conclusions
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