Up

Design Automation Technologies for Realizing Reconfigurable Computing Systems

Abstract

We are seeking to find suitable forms of concurrent architecture from the standpoint of design automation technologies. We are particularly interested in programmable logic devices to realize efficient reconfigurable computing (RC) systems by dynamically changing logic structures to fit the given application.

Background

The RC system is a flexible hardware system with logic structure that can be changed using programmable logic devices such as field programmable gate arrays (FPGAs). We expect the system will have extremely high-performance with structures that can be flexibly adapted to each application by static or dynamic reconfiguration. To achieve reconfigurable computing systems, design automation technologies (e.g. synthesis and mapping for effective reconfiguration mechanism and logic functions) are very important.

Design Automation Technologies

We have been researching the design automation system, PARTHENON (Parallel Architecture Refiner Theorized by NTT Original Concept)[1],[2] together with feasible hardware architecture suitable for these design automation technologies. The architecture and design technologies of RC systems are inseparably related so they should be simultaneously investigated.

Up to now, we have worked on static reconfiguration and research on essential technologies such as estimation of RC architectures and logic synthesis technologies for FPGAs [3].

Ultimately, the goal of our research is to develop dynamic RC systems, and we believe the device for the system should have a basic structure for reconfiguration besides a logic structure. We plan to expand our technologies in order to establish a design automation system and to realize dynamic reconfiguration in such devices (Fig. 1).

Fig. 1: Devices and design flow for dynamic RC systems
Fig. 1: Devices and design flow for dynamic RC systems

References

[1]
Nakamura, Y., Oguri, K., Nagoya, A., Yukishita, M. and Nomura, R.: High-Level Synthesis Design at NTT Systems Labs, IEICE Transactions on Information and Systems, Vol. E76-D, No. 9, pp. 1047-1054 (1993).
[2]
PARTHENON Home Page, http://www.kecl.ntt.co.jp/parthenon/.
[3]
Nagoya, A.: Design Automation Technologies for Realizing Novel Concurrent Architecture (in Japanese), NTT R&D, Vol. 46, No. 2, pp. 153-158 (1997).

Contact: Akira Nagoya; Email: nagoya@cslab.kecl.ntt.co.jp